1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device using a MOS transistor.
2. Description of the Related Art
In a semiconductor memory device which employs an FN tunnel current for injecting charge into a floating gate, application of an electric field of approximately 10 Mv/cm to a gate insulating film is needed to induce the FN tunnel current flow. Further, the electric field that is actually needed becomes approximately 12 MV/cm to control the potential of the floating gate from the potential of the control gate. As to a MOS transistor used in an ordinary circuit, the electric field that may be applied to the gate insulating film is at most between 4 and 6 MV/cm for insuring a typical life time of ten years. Accordingly, formation of a special gate insulating film, which is distinct from a gate insulating film used in other elements and which is able to withstand the strong electric field, is required as a gate insulating film in which the FN tunnel current flows. Consequently, there is a problem of increase in the number of manufacturing steps. For that reason, the nonvolatile memory device employing the FN tunnel current is often sold in the form of a single nonvolatile memory device on the market.
Other than above, there is provided a memory device in which a hot carrier of the MOS transistor is utilized for injecting the charge into the floating gate so that data can be kept by shifting the Vth. This memory device is used for trimming in many cases since the memory device does not need special manufacturing steps used in the nonvolatile semiconductor memory device device is used for a trimming of an LCD driver IC, a power supply IC and the like. It is because the nonvolatile semiconductor memory device, which uses the hot carrier, can be formed on the same chip without any additional steps in the manufacturing steps for those products.
If an NMOS, which has a relatively large impact ionization ratio, is used, the Vth of the NMOS transistor in which no charge is injected into the floating gate, i.e., writing is not made is depletion and is normally on. In contrast, when the charge is injected into the floating gate, i.e., writing id made, the Vth becomes enhancement, i.e., normally off. In the reading operation, in which the control gate is set low while a voltage is applied between the drain and the source, current does not flow between the drain and the source in the NMOS transistor that is written while current flows between the drain and the source in the NMOS transistor that is not written. The current flow between the drain and the source causes the generation of the hot carrier, and a part of the hot carrier is injected into the floating gate though the injection is extremely little. In other words, the reading operation advances the writing as time passes. In order to solve this problem, various structures have been made (see, for example, Japanese Patent Application Laid-open JP 10-189918).
Other than the memory device described above there is proposed a memory device in which a voltage higher than or equal to the junction withstanding voltage is applied to the diode to short-circuit the junction for writing. Since application of the same voltage in the reading operation as that in the writing operation short-circuits the junction so that the writing is made in this method, the reading voltage is suppressed to be low. Alternatively, it is necessary to perform the writing by applying a voltage higher than or equal to the maximum operating voltage. In addition, it is difficult to form the diode having the withstanding voltage satisfying the above-mentioned condition on the same substrate without adding a manufacturing step in many cases (see Japanese Patent Application Laid-open JP 6-139778).
There are various means taken for avoiding the injection of charge into the floating gate during the reading operation in a semiconductor memory device that utilizes the hot carrier in writing. For instance, a lightly doped drain (LDD) structure is used to relax the electric field in the vicinity of the drain so as to suppress the hot carrier in the reading operation. This countermeasure reduces injection of the charge into the floating gate, but can not be an essential solution. There is taken another countermeasure in which the drain voltage for reading is restricted to a voltage lower than that for writing so as to avoid an erroneous writing because continuous application of the same voltage for reading as that for writing causes erroneous writing in a MOS transistor that is not written. Further, there is the case where data is acquired at the turning-on of the power so as to reduce time duration for applying the voltage for reading, and the data is stored in the SRAM so that the voltage is applied only at the turning-on of the power. Such a countermeasure has a problem that the operating voltage range becomes narrow or that the area of the chip increases because of the additional circuit.
In addition, in the semiconductor memory device using a short-circuit in the junction of the diode the suppression of the reading voltage to be low or the application of a voltage higher than or equal to the maximum operating voltage for writing is needed because the application of the same voltage in reading as that in writing causes the short-circuit in the junction by which writing occurs.
For the reason described above, a memory device has been demanded, in which writing is performed by a voltage within the maximum operating voltage that is determined by the MOS transistor other than the memory element, and data inversion does not occur even if the maximum operating voltage determined by the MOS transistor other than the memory element is applied continuously for a desired period of time, e.g., ten years typically. In addition, a method of manufacturing such a memory device has been demanded, which does not need additional steps and may be realized at low cost.